Luis Y. Hernandez

Pipelined Processor Design

Pipelined MIPS Architecture

Image credit: Pipelined MIPS Architecture by Tadi Chandrasekhar

Simple Processor Design in Verilog

This project’s goal is to implement and design a 5-stage pipelined CPU in Verilog. The project is divided into three stages, each building on the previous one to add more complex instruction sets and control logic.

Stage 0:
Lays the foundation by implementing the logic for each pipeline stage, including instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and write-back (WB). It also includes a basic controller that supports simple instructions like ADDI (Add Immediate) and B (Unconditional Branch).
View Stage 0 on EDA Playground

Stage 1:
Expands the instruction set to include ADD (Add), SUBI (Subtract Immediate), and CBZ (Compare and Branch if Zero), introducing more complex branching logic and enhanced control signal management.
View Stage 1 on EDA Playground

Stage 2:
Further refines the design with support for BL (Branch and Link) and BR (Branch to Register), adding subroutine capabilities and more flexible control flow.
View Stage 2 on EDA Playground

Each stage includes a testbench for verifying functionality and performance, ensuring the processor can handle a wide range of instruction types while maintaining efficient pipeline flow.

Key Components:

Program Counter Logic:

This section of the code implements the Program Counter (PC) logic for the Instruction Fetch (IF) stage in the pipelined CPU. The PC is responsible for tracking the address of the next instruction to be fetched from memory. It is updated on each clock cycle and plays a critical role in managing the flow of the program.

There are several key components to the Program Counter Logic, which are expanded in later stages of the project. However, in this stage, we focus on two main features:

This foundational logic sets the stage for more complex control flow in later stages, including support for subroutine calls and conditional branching.

Instruction Decode / Register Fetch:

This section of the Verilog code implements the Instruction Decode (ID) / Register Fetch stage of the pipelined CPU. It uses a packed struct called IFID to pass data from the Instruction Fetch (IF) stage to the Instruction Decode (ID) stage, ensuring that both the program counter (PC) and instruction are treated as a single unit.

Key Features:

This stage is crucial for ensuring efficient data flow through the pipeline, setting the stage for ALU operations and branching in later stages.

Execution and Address Calculation

This part of the code implements the IDEX pipeline register, which is responsible for holding the control signals and data as they pass from the Instruction Decode (ID) stage to the Execute (EX) stage. This is where the actual computation happens, including ALU operations and branching decisions.

The IDEX register captures critical control signals like branch, regWrite, aluSrc, and aluSel, along with the current program counter (pc), instruction (instr), and operand data (readData1, readData2). It ensures that all necessary information is available for the ALU and other components to make accurate calculations.

This part of the execute stage handles two critical components: the MUX for register index selection and the ALU (Arithmetic Logic Unit). These components are responsible for selecting the destination register, preparing the ALU operands, and performing the actual computation.

Key Components:

Together, these components form the core of the EX stage, ensuring that the CPU can efficiently execute a wide range of instructions with minimal delay.

Memory Access (MEM)

This section of the code implements the Memory (MEM) stage of the pipelined CPU. It includes the EXMEM pipeline register, the main data memory, and the logic for reading and writing data during this stage. This is where the CPU interacts with data memory, loading values from or storing values to memory based on the instruction type.

Key Features:

Core Components:

Together, these components form the backbone of the MEM stage, ensuring efficient data handling and memory access for the pipelined CPU.

Write Back (WB)

This part of the code implements the Write Back (WB) stage of the pipelined CPU. This is the final stage of the pipeline, where the results of computations or memory reads are written back to the register file, completing the instruction execution cycle.

Key Features of the WB Stage:

Together, these features ensure that the WB stage completes the final step of instruction execution efficiently, supporting a wide range of instruction types while minimizing data hazards.

Controller

This section of the code implements the Controller for the CPU, which is responsible for generating the control signals that guide the operation of each pipeline stage. It uses a case statement to decode the opcode of the current instruction and set the appropriate control signals accordingly.

Key Features of the Controller:

Together, these features make the controller a critical part of the CPU, allowing it to efficiently decode and execute a wide range of instruction types.

Supported Instructions

Instruction Opcode Description
ADD 0 Register addition
SUB 1 Register subtraction
B 2 Unconditional branch
LD 3 Load from memory
ST 4 Store to memory
CBZ 5 Compare and branch if zero
ADDI 6 Add immediate
ANDI 7 AND immediate
SUBI 8 Subtract immediate
BL 9 Branch and link
BR 10 Branch to register

This CPU supports a range of basic instructions, including arithmetic, logical, memory access, and control flow operations. These instructions form the core functionality of the processor, allowing it to perform a wide variety of tasks.

Instruction Categories:

Key Features:

These instructions are the building blocks for implementing more complex algorithms and programs, making this CPU versatile for a wide range of applications and a great learning tool.